Aegis – open-source FPGA silicon

smj-edison 31 minutes ago | parent | next [-]

As someone who has only dabbled with FPGAs before, this is incredible to see all the steps end-to-end for silicon development! I feel like the articles I've read always leave out details in one part or another, so it's interesting to see all the nix dependencies and build steps.

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dizhn 4 hours ago | parent | prev | next [-]

There's also an open source Authenticator software with the same name.

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mosaibah 2 hours ago | parent | prev | next [-]

The gap this closes is real. IceStorm and Apicula gave you open tooling but you were still loading bitstreams onto someone else's closed fabric. Yosys/nextpnr same story. Aegis is the first time the fabric itself is auditable, which matters a lot for anyone building hardware that needs a complete trust chain from RTL down to GDS. The wafer.space + open PDK path makes it actually tapeout-able, not just a simulation exercise. Curious how the LUT4 fabric competes on density against GF180 commercial offerings, that's usually where open implementations get humbling

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Bluebirt 6 hours ago | parent | prev | next [-]

Neat project - there are already a couple of good open FPGA projects. Have a look at Dirk Koch's and the FABolous teams work. They are doing exceptional work.

But all open FPGA projects miss the IO required for a good design. They do not have any serdes hardware nor DDR IO cells.

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rosscomputerguy 44 minutes ago | parent | next [-]

Yeah, I did see there's been attempts but none really satisfied what I wanted out of it. I do know of FABulous and it seems good but not quite what I wanted. You can see that aside from yosys and nextpnr, it is quite self contained and even provides a very easy way of defining new silicon with Nix.

I know that IO is really the 2nd thing which sells FPGA's. I did design a basic serdes hardware that should just work for this first generation. I do want to do DDR IO cells in the future.

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LarsKrimi 5 hours ago | parent | prev [-]

This project seems to have a serdes block which seems to wrap whatever is in the PDK. Didn't look too far down but from a cursory glance it looked like it was built for an internal clock of 50 MHz (clock default to 20 ns) with an oversampling of 8: 400 MHz

If those numbers are at all right it puts it in useful territory. Very much so for a first spin

For a first spin it looks overall pretty useful. The only nitpick I have would be that `operation` on the DSP tile should be from fabric instead of config (hardcoded in bitstream) otherwise I don't see a convenient way of resetting the accumulator(?)

	▲	rosscomputerguy an hour ago \| parent [-]
		Thanks for the suggestion on the DSP. Maybe I'll add new DSP tiles that are reconfigurable and keep the config based DSP tiles. I designed Aegis's Terra 1 to be a "good enough first gen" so that's why things are the way they are. I didn't want to over commit on the design for a first generation.

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blowback 7 hours ago | parent | prev [-]

Excellent. Put me down for a couple.