I want to fix this, could you elaborate a bit (would help even more if you pressed the copy circuit and pasted the result here)

Add 2 AND gates, 1 NOT gate

G0 = D0 AND SEL

G1 = NOT SEL

G2 = D1 AND G1

G0 -> Ans

G2 -> Ans

	▲	Jaso1024 5 hours ago \| parent [-]
		oh its b/c of the contention between the outputs of the ands for the answer, u need an or gate to merge them (ill add an update w/ visual feedback for these sorts of thigns)