The 4 values in MaxSrcRectWidthForPipe are sub-pipes within each display controller, not separate display outputs. Every external display controller on the M5 Max has the same pattern: sub-pipe 0 = 6720, sub-pipes 1-3 = 7680. A single-stream 4K display only uses sub-pipe 0. Sub-pipes 1-3 are for multi-pipe configurations (8K displays use 2 sub-pipes, which is why an 8K EDID causes the DCP to assign PipeIDs=(0,2) with MaxPipes=2).

Your scaler clock theory could be right: the single-stream scaler path may genuinely have a lower throughput limit than the multi-pipe path.

Interestingly, the M2 Max uses a completely different IOMFBMaxSrcPixels structure. Instead of per-sub-pipe arrays, it has a flat MaxSrcRectWidth=7680 and MaxSrcRectTotal=33177600 (exactly 7680x4320) per controller. Every external display controller gets the full 7680 budget. Apple seems to have restructured the display controller architecture between M2 and M4/M5 to per-sub-pipe budgets, and the single-stream sub-pipe got a reduced allocation (6720 vs 7680) in the process. Whether that's a hardware change in the scaler or a firmware allocation policy is hard to say without Apple's documentation.