Draw yourself an SR latch and try simulating. Or a circuit what is known as „pulse generator“

hardolaf 11 hours ago | parent | next [-]

Both SystemVerilog and VHDL have AMS extensions for simulating analog circuits. They work pretty well but you also pay a pretty penny for the simulator licenses for them.

▲

CorrectHorseBat 17 hours ago | parent | prev [-]

Those are analog circuits, if you put them in your digital design you are doing something wrong.

▲

kryptiskt 12 hours ago | parent | next [-]

All circuits are analog when physically realized, the digital view is an abstraction.

▲

artemonster 11 hours ago | parent | prev [-]

dont know if trolling. SR latch you can do with 2 NANDs, or NORs there are plenty of *digital* circuits with that functionality, and yes, there are very rare cases when you construct this out of logic and not use a library cell for this. pulse circuit is AND(not(not(not(a))),a) also rarely used but used nonetheless. to properly model/simulate them you would need delta cycles

	▲	CorrectHorseBat 9 hours ago \| parent [-]
		I'm not sure if you are trolling. 99.999% of digital design is "if rising edge clk new_state <= fn(old_state, input)", with an (a)sync reset. The language should make that the default and simple to do, and anything else out of the ordinary hard. Now it's more the other way around.