| ▲ | jitl 7 hours ago | |||||||||||||
Really? Pretty much all atomics i’ve used have load, store of various integer sizes. I wrote a ring buffer in Go that’s very similar to the final design here using similar atomics. | ||||||||||||||
| ▲ | dalvrosa 6 hours ago | parent | next [-] | |||||||||||||
Nice one, thanks for sharing. Do you wanna share the ring buffer code itself? | ||||||||||||||
| ▲ | wat10000 6 hours ago | parent | prev [-] | |||||||||||||
They generally map directly to concepts in the CPU architecture. On many architectures, load/store instructions are already guaranteed to be atomic as long as the address is properly aligned, so atomic load/store is just a load/store. Non-relaxed ordering may emit a variant load/store instruction or a separate barrier instruction. Compare-exchange will usually emit a compare and swap, or load-linked/store-conditional sequence. Things like atomic add/subtract often map to single instructions, or might be implemented as a compare-exchange in a loop. The exact syntax and naming will of course differ, but any language that exposes low-level atomics at all is going to provide a pretty similar set of operations. | ||||||||||||||
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