> Hierarchical physical design tends to be worse than flat PD because there are many variables to optimize (placement density, congestion, IR drop, thermal, parasitics, signal integrity, di/dt, ...) and even if you have some solution in mind that optimizes area for a highly regular block, that layout could be worse than a solution that intersperses lower-power cells throughout that regular logic to reduce hotspots.

This paragraph goes hard. And this is exactly why design space exploration is essential. I think you're right that basically, simplistic delay/area models are insufficient and the exploration must be driven by actual metrics of complete P&R flows.

> [...] it's a pretty challenging problem to design a formal specification language that is simultaneously high level enough and yet allows a compiler to do a good job of finding the optimal chip design

My experience in this domain is that actually the challenging problem isn't so much the design of a formal language. Instead the challenge lies primarily in expressing your design in such a way that both generalizes over and meaningfully exposes the freedom in the design space.

> [...] solving the problem of "what is the most efficient way to approximate this algorithm with N% precision"

> [...] in many domains it's hard to formulate an error metric that isn't either too conservative or too permissive.

I think the latter comment alludes to my objection about the former: It all depends on what "N% precision" means.

Does it mean that for every input/output pair, the output is always within N% of the correct value?

Or does it mean that for N% of the inputs, the output is correct? Is that weighted by the likelihood distribution of getting those inputs?

Or does it mean that the total mean squared error over all input/output pairs is within N%? Etc. etc.

In other words, I think it goes beyond even conservative vs. permissive; simply, the devil is in the details, and digital circuit design is a difficult multi-objective optimization problem.