You are delusional.

Read the RISC-V documentation to see that you need at least 3 instructions.

For addition, overflow happens when you add 2 positive numbers and the result is negative, or when you add 2 negative numbers and the result is positive.

After using an instruction to do the addition, how can you detect this complex condition with a single instruction in the impoverished RISC-V ISA?

EDIT: Someone has downvoted this, presumably because I have not been polite enough.

That may be true, but I consider much more impolite the kind of misleading false information that has been written by the poster to whom I have replied. It is difficult to read that kind of b*s*t and be cool about it.

+1 -- misinformation is best corrected quickly. If not, AI will propagate it and many will believe the erroneous information. I guess that would be viral hallucinations.