Well for DDR5 that's 25% more chips which isn't great even if you don't get ripped off by market segmentation.

It's possible DDR6 will help. If it gets the ability to do ECC over an entire memory access like LPDDR, that could be implemented with as little as 3% extra chip space.

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hikarudo 12 hours ago | parent [-]

Why 25%, shouldn't it be 12.5%? 8 ECC bits for every 64 bits.

	▲	ciupicri 11 hours ago \| parent [-]
		DDR5 ECC RDIMMs (R=registered) have 16 extra bits. From the specifications for Kingston's KSM64R52BS8-16MD [1]: > x80 ECC (x40, 2 independent I/O sub channels) On the other hand ECC UDIMMs (U=unbuffered) have only 8. From the specifications for Kingston's KSM56E46BS8KM-16HA [2]: > x72 ECC (x36, 2 independent I/O sub channels) Though if I remember correctly, the specifications for the older DDR4 ECC RDIMMs mention only 72 bits. [1]: https://www.kingston.com/datasheets/KSM64R52BS8-16HA.pdf [2]: https://www.kingston.com/datasheets/KSM56E46BS8KM-16HA.pdf