Very nice. I might steal some ideas.

A small comment after a cursory look: the signaling in CoroTracer.h:162 is susceptible of missed wakeups; you would need a #StoreLoad fence between the slot .seq store and the sleeping flag load (and for the load to be an acquire). The traces probably needs a mirror change.

As the load is relaxed, I assume you are not worried by missed wakeups and it is ok if the tracer is woken up by a latter trace. Of course there might not be a latter trace and you would need a timeout on the sleep.

Thanks for the catch! You’re spot on about the missed wakeups. It's still a very early prototype—mainly just wanted to see if this whole architecture holds water. I'll definitely be adding the #StoreLoad fence and tightening up the memory ordering in the next push. Appreciate the feedback!