| ▲ | hansvm 3 hours ago | |
I've observed the same behavior on AMD and Intel at $WORK. Our solution (ideal for us, reads happening roughly 1B times more often than writes) was to pessimize writes in favour of reads and add some per-thread state to prevent cache line sharing. We also tossed in an A/B system, so reads aren't delayed even while writes are happening; they just get stale data (also fine for our purposes). | ||
| ▲ | the_duke 2 hours ago | parent [-] | |
Rust has an interesting crate for this, arc-swap [1]. It's essentially just an atomic pointer that can be swapped out. | ||