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Cyph0n 5 hours ago

Thanks for clarifying. HN is ~generally more software centric, so this context is helpful.

So SPICE is a low-level circuit sim, and PLECS is a bit higher level as it ignores non-linearities at the device level. Does PLECS simulate at a level similar to that of the popular EDA tools like Cadence?

eschu 4 hours ago | parent [-]

Roughly speaking yes, but Cadence has a large offering of products, so I need to be a little more specific. Ultimately, when you design analog devices with Cadence's tools, their transient behavior is simulated by Spectre (or FastSPICE) for IC (very) low-level analog validation. This is still SPICE, but with an engine really tailored for reading Verilog-A or large netlist descriptions (a format to describe circuits with plain text). Let's call this level 1.

They also have PSpice. Here, we are already speaking mixed-signal (including digital) for board-level simulation and systems. It competes with the likes of QSpice, the very popular Ltspice, SIMetrix etc. This is level 2.

Before PLECS or SIMPLIS, system-level designs that include controller, power-plant, thermal behavior and magnetics were also simulated with those tools. PLECS went one more level of abstraction higher so that all these systems could be simulated together (including say the power-train of a power electronic system that comprises battery to wheels of an electric car). This is level 3. Think of it like Simulink (MATLAB) but dedicated to the challenges of power electronics (high frequencies are difficult to simulate with general off-the-shelf simulators).

What is new now is that within PLECS, you can import SPICE netlists, effectively enabling level 2 and 3 within one tool, and even to some extent together in the same simulation run (ideal switches coexisting with SPICE models). So you can design top-down. You start from the system, and then deep dive by replacing, in some sub-circuits you care about, the PLECS ideal switches by the detailed SPICE models of your real devices. These are often provided by semiconductor manufacturers (and they may have been generated by an analog design tool from Cadence).