| ▲ | rep_lodsb 10 hours ago | ||||||||||||||||||||||
The 80186 and NEC Vxx chips - and of course also the 286 - could already do mul/div in one cycle per bit (+ some overhead for the microcode). What they didn't have was the early-out optimization. The three-operand form of IMUL also already existed on those processors. >This wasn't just an incremental upgrade—it was the foundation that would carry the PC architecture for decades to come. AI? | |||||||||||||||||||||||
| ▲ | ack_complete 2 hours ago | parent | next [-] | ||||||||||||||||||||||
The timeline for fast multiplies is also a bit off, IMUL was already 4c latency / 1c throughput on the Pentium Pro (1995) and Pentium II (1997). Pretty sure IMUL was also only a few cycles on the AMD K6 (1997). Though Intel slowed it back down again in the Pentium 4, until they reverted back to the P6 architecture in the Pentium M. | |||||||||||||||||||||||
| ▲ | csmantle 10 hours ago | parent | prev | next [-] | ||||||||||||||||||||||
> AI? Probably not; this point is well justified by both theory and practice. Supporting suitably larger operands is indeed what naturally comes following the increase of computation demands. One point I do differ from the author is that register width don't necessarily correlate with the size of address space. Even 8bit machines can address a large space by splitting apart the logical address and using multiple registers. Likewise, having a wide register does not imply the same address width. | |||||||||||||||||||||||
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| ▲ | 9 hours ago | parent | prev [-] | ||||||||||||||||||||||
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