> Where is the RTL? Where are the GDSII masks? Why am I unable to look at the branch predictor unit in the Github code viewer? Or (God forbid!) the USB/HDMI/GPU IP? I reject the notion that these are unreasonable questions.

As you note correctly, the ISA is open, not this CPU (or board).

The important point is that using an open ISA allows you to create your own CPU that implements it. This CPU can then be open (i.e. you providing the RTL, etc.), if you so desire

I assume it will be much more difficult (or impossible?) to provide the RTL for a CPU with an AMD64 ISA, since that one has to be licensed. I wonder if you paying for the license allows you to share your implementation with the world. Even if it does, it's less likely that you will do so, given that you will have to pay for the licensing fee and make your money back

Since there is no license to pay for in case of RISC-V, it allows you to open up the design of your CPU without you having to pay for that privilege

My superficial understanding is that arm does not prevent from sharing implementation details of your own design but most chips also license a starting implementation that has such limitations. So the end result is often more restricted than the ISA licence some would require