4 MB of SRAM in the '80s would have been the main RAM of a supercomputer.

We still use SRAM today. It's what level-1 cache and registers are implemented with - actual flip-flops, can be toggled with one cycle delay. Supercomputers used to make their entire main memory out of SRAM, effectively the whole thing was L1 cache.

The 486 has an on-chip cache - 8 or 16 KB of SRAM. Very large for the time.

Off-chip access to the DRAM involves wait states. The read or write is stalled until the DRAM enters the appropriate state. The 486 would also do block reads of 16 bytes at a time to fill an entire cache line. This is around the time main memory and the CPU became increasingly decoupled.

Avoiding all the complexity of managing DRAM is why hobbyists use SRAM these days. Basically: to avoid cost. Ironic!

And large amounts of L1 cache do in fact cost a fortune today!