>They often support different instruction sets than their P-cores

Do they?

I thought it caused very significant problems (when there's switch between E and P core) and they avoided it

But I cannot find anything about it

The P and E cores support different instructions and Intel "fixed" it by disabling instructions on the P-cores. So now they have the same instructions but at the cost of a bunch of wasted silicon.

The Intel server CPUs with P-cores support AVX-512, like all current AMD CPUs, and they also support a few extensions not currently supported by AMD, like AMX (Zen 6 will add FP16 arithmetic support in AVX-512, reducing the differences vs. Intel P-core servers).

The Intel server CPUs with E-cores, both the current Sierra Forest CPUs with Crestmont cores and the future Clearwater Forest CPUs with Darkmont cores do not support AVX-512 and they are almost identical with the E-cores from Intel laptop/desktop CPUs.

Therefore, for demanding applications you cannot run the same programs on Intel servers with P-cores or E-cores, unless they use dynamical dispatch to select at run-time between AVX and AVX-512 libraries, as the gain from AVX-512 can be very substantial and on server applications not using it would lose money by lowering the throughput.

The Intel Darkmont cores of Panther Lake and Clearwater Forest are almost identical with the Skymont cores of Arrow Lake and Lunar Lake (the main difference is that the Skymont cores are made by TSMC, while the Darkmont cores are made by Intel in their new 18A CMOS process) and they are extremely similar in die size and in performance with the ARM Neoverse V3 cores from the newly launched AWS Graviton5 (which are known as Cortex-X4 in their smartphone variant).

Intel has said that they will eliminate this ISA difference between E-cores and P-cores, but a couple of years might pass until this will reach their server CPUs.

> Do they?

Yes?