This article is a rant about how bad tools are without going into specifics. "VHDL and Verilog are relics", well so is "C" but they all get the job done if you've been shown how to use them properly.

"engineers are stuck using outdated languages inside proprietary IDEs that feel like time capsules from another century.". The article misses that Vivado was developed in the 2010's and released around 2013. It's a huge step-up from ISE if you know how to drive it properly and THIS is the main point that the original author misses. You need to have a different mindset when writing hardware and it's not easy to find training that shows how to do it right.

If you venture into the world of digital logic design without a guide or mentor, then you're going to encounter all the pitfalls and get frustrated.

My daily Vivado experience involves typing "make", then waiting for the result and analysing from there (if necessary). It takes experience to set up a hardware project like this, but once you get there it's compatible with standard version control, CI tools, regression tests and the other nice things you expect form a modern development environment.

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CamperBob2 34 minutes ago | parent | next [-]

"VHDL and Verilog are relics", well so is "C" but they all get the job done if you've been shown how to use them properly.

Or how to use an LLM properly.

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tverbeure 3 hours ago | parent | prev [-]

> My daily Vivado experience involves typing "make", …

Exactly my experience with Quartus as well.

One really can’t help but wonder if those who always whine about the IDE/GUI just don’t know any better?

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Cadwhisker 2 hours ago | parent [-]

I've managed to make nice 'make' flows for Vivado, ISE, Quartus and DC. Libero took a bit more poking, but it's also possible.

The GUI interfaces are what newcomers tend to aim for straight away, but they're not good for any long-term "repeatable" build flows and they're no use for CI. I think this is where a lot of the frustration comes from.

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fooblaster 2 hours ago | parent [-]

I think my real problem is that xilinx pushes the gui flows heavily. It is extremely annoying to configure the mpsoc fabrics entirely outside of vivado. Same thing for using any of their bundled IP.

	▲	Cadwhisker an hour ago \| parent [-]
		Yes, IP usage is awkward and tricky. You can use the GUI to make the initial .xci file or .tcl file, but when you build a project, you need to use the same version of Vivado that the IP core was originally created in. Xilinx have improved that a little with 'write_ip_tcl' and 'write_bd_tcl' now having flags that let you ignore the version (or minor version). I've not had time to try those yet.