They said the same thing about 40G but hey, I've loved it for bridging the gap between my two (10G and 100G, respectively) Mikrotik switches. You can have a dozen Gigabit ports, as well as up to four true 10G devices on your aggregation switch, and neither would be bottlenecked by traffic to and from the backside. This has been a massive boon. However, when it comes to 2.5G, I struggle to find one good reason to use it; such a tiny step-up in bandwidth, and for what?

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JoshTriplett 2 hours ago | parent | next [-]

> However, when it comes to 2.5G, I struggle to find one good reason to use it; such a tiny step-up in bandwidth, and for what?

Portability and heat. You can get a small USB 2.5G adapter that produces negligible heat, but a Thunderbolt 10G adapter is large and produces a substantial amount of heat.

I use 10G at home, but the adapter I throw into my laptop bag is a tiny 2.5G adapter.

	▲	johncolanduoni 2 hours ago \| parent [-]
		I’m sure it depends on the model, but in my experience if you force a 10G copper transceiver to 2.5G the insane heat generation goes away. I don’t have any Thunderbolt 10G adapters, but I’m kind of surprised they’re much larger. A SFP+ transceiver is the same size as a SFP one.

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johncolanduoni 2 hours ago | parent | prev | next [-]

40G on Mikrotik is just channel bonding of 4 10G links at layer 2. It’s not like the vast majority of 100G that does layer 1 bonding. I really don’t know why they did it other than to have a bigger number on the spec sheet - I can’t imagine they save any money having a weird MAC setup almost nobody else uses on a few low-volume models.

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u8080 2 hours ago | parent | prev [-]

1x PCIE 3.0 has 8 Gbps raw speed - for 2.5Gbps duplex Ethernet you'll need 6~7 Gbps of raw link to CPU.

For 5Gbps and higher, you'll need another PCIE line - and SOHO motherboards are usually already pretty tight on PCIE lanes.

10GbE will require 4x3.0 lanes

	▲	johncolanduoni an hour ago \| parent [-]
		Are motherboards commonly using PCIe 3.0 for onboard peripherals these days? I wouldn’t expect it to save them much money, but my PCIe knowledge is constrained to the application layer - I know next to nothing about the PHY or associated costs.