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Show HN: An LLM-Powered Tool to Catch PCB Schematic Mistakes(netlist.io)
25 points by wafflesfreak 4 hours ago | 19 comments
swatcoder 3 hours ago | parent | next [-]

Where's the performance data?

Anybody can send a PCB description/schematic into an LLM, with a prompt suggesting it generate an analysis and it will diligently produce a document that perceptually resembles an analysis of that PCB. It will do that approximately 100% of the time.

But making an LLM actually deliver a sound, useful, accurate analysis would be quite an accomplishment! Is that really what you've done? How did you know you got it right? How right did you get it?

To sell an analysis tool, I'd expect to see some kind of comparison against other tooling and techniques. General success rate? False negative rate? False positive rate? How does it do against simple schematics vs large ones? What IC's and components will it recognize and which will it fail to recognize? Does it throw an error if it encounters something it doesn't recognize? When? Do you have testimonials? Examples?

proee 2 hours ago | parent [-]

I'm sure your feedback is appreciated, but the tone of your reply is a skeptical engineer with arms crosses. This is a show HN post, and we should support the founder(s) if we think this is a good idea. Clearly a MVP product is not going to check all your boxes, but does it have the potential to be really useful?

I see this idea as a sort of AI ERC/DRC checker that offers some incredible opportunities. Even if it only catches one small, it could save thousand of dollars down the line.

It's another tool in the toolbox for hardware designers.

achr2 2 hours ago | parent [-]

>> Even if it only catches one small, it could save thousand of dollars down the line.

Or it could send a design team down thousands of dollars in false positives/false negatives. With zero benchmarks provided, it is very fair to question a product that could have material negative impacts on a hardware team.

proee 2 hours ago | parent [-]

The tool would ideally classify the output into levels. Just like a compiler or DRC checker. If you submit a clean design, the tool should not be throwing major flags. 99% of the time you should be getting advisory outputs, which should not be tricking any designer. The 1% red flags should easily be understood and if you, as the designer, can't discern them, perhaps you don't understand the fundamentals of your own design.

ProllyInfamous 3 hours ago | parent | prev | next [-]

Would this catch physical interference issues from known components? e.g. conflict spacing, connector pin-out chirality?

I know a brilliant PCB engineer whose first major multimillion dollar R&D corporate design (decades ago) resulted in production of a modular product which couldn't physically plug in with the rest of the system (because of above issues)... I'll send him this link to see if he'll give you feedback, but that's going to be how he'd initially test your AI system (he considers it a humbling lifetime blunder).

Without any PCB design experience, my presumption is that OP's "AI product" is more of just a "fundamentals of circuit board design"[0] and not an all-expansive "how did no human ever catch such a simple multi-dimensional clash"[1]

[0] isolated voltage areas; trace attenuation avoidance; signal protection

[1] the darn thing won't even plug in, because the plug is pin'd-out backwards

wafflesfreak 3 hours ago | parent | next [-]

Hi! Great question. Right now the tool focuses on issues that show up in the schematic. So it’s very well-equipped to handle a lot of the classic “how did no human ever catch this” mistakes — things like reversed polarity, TX/RX getting swapped, missing pull-ups, etc.

But it sounds like in this case the root cause was more of a footprint/layout issue rather than a schematic one. I’m hoping to add footprint-level checks later on, once I can ingest full board files and mechanical data.

rasz an hour ago | parent | prev [-]

This is a solved problem nowadays. Pretty much every pcb package produces 3D models you can plug into your existing CAD/CAM product design infrastructure.

exmadscientist an hour ago | parent [-]

3D is pretty solved, yes.

Pinouts... there is a reason we try to get all pinouts tested as early as possible, preferably on the first non-form-factor prototype spin if we can. In no event should key pinouts be first assigned or major changes made without a planned spin in the schedule following them....

wafflesfreak 4 hours ago | parent | prev | next [-]

Netlist.io is a web app that ingests your KiCad/Altium netlist and relevant datasheets so an LLM can reason about the actual circuit. It’s built to catch schematic mistakes that traditional ERC tools often miss, and it can even help debug already-fabbed boards by letting you describe the failure symptoms.

I built this because I was tired of shipping boards with avoidable mistakes — hopefully it saves you from a re-spin too!

throwaway31131 30 minutes ago | parent [-]

Ingesting data sheets is an interesting angle compared to normal ERC, which KiCAD supports out of the box, but how good is it at the ingesting?

Datasheets themselves are inconsistent and incomplete so I’m wondering how you evaluated the accuracy of the import and what your acceptance criteria is.

proee 4 hours ago | parent | prev | next [-]

Back in the day our hardware group created a pre-flight checklist before sending boards off to fab. This reduced our errors significantly and got rid of stupid mistakes. Your product idea sounds great and has ton of opportunity for additional features like supply chain analysis, alternate part sourcing, EMC advisory, etc.

wafflesfreak 4 hours ago | parent [-]

Thank you so much! Totally agree. Knowing people in the space to sanity-check designs has saved me countless times. I’m hoping this tool can bring some of that ‘pre-flight checklist’ group wisdom to solo and newer designers as well. Really appreciate the feature ideas too!

throwaway31131 26 minutes ago | parent [-]

Isn’t the primary issue that newer designers don’t know they show run ERC (or that ERC even exists)? Isn’t your tool going to have the same issue? i.e. how do user even know they should run it in the first place? How do you plan to overcome that barrier?

I’m not against more automated checkers, I’m very much for automated checkers, but I’m curious how you plan to not repeat the mistakes of the past.

noshitsherlock 3 hours ago | parent | prev | next [-]

Would this tool be able to accommodate vacuum tube designs and the associated schematics, either point to point. Or PCB?

wafflesfreak 3 hours ago | parent [-]

Hi! If the vacuum tube schematic is designed in KiCad or Altium, then yes! If your design was made in another tool let me know which one and I will do my best to add support for it.

iamjackg 4 hours ago | parent | prev [-]

Somewhat related: a while ago I was working on a project and wanted to use an RS485 to TTL conversion board which came with badly translated instructions. However, somebody had reverse engineered the design and uploaded an EasyEDA schematic. I shoved the raw JSON for the schematic (which looked quite cryptic to me) into Gemini 2.5 Pro and asked it if it could understand it, and it cheerfully responded with:

> Of course, Jack. I can understand the schematic from the provided JSON file. It describes an RS485 to TTL Converter Module. > Here is a detailed breakdown of the circuit's design and functionality

...followed by an absolutely reasonable description of the whole board. It was imprecise, but with some guidance (and by putting together my basic skills with Gemini's vast but unreliable knowledge) I was able to figure out a few things I needed to know about the board. Quite impressive.

wafflesfreak 3 hours ago | parent | next [-]

I had a really similar experience, which is a big reason why I built this. Uploading my own schematics to the usual web LLMs gave a mix of useful notes and some pretty big misunderstandings. I really believe this tool is set up to deliver better results than the general-purpose GPT/Gemini/Claude interfaces for this kind of task. Hoping others try it and have a much better experience too!

Also good call on processing EasyEDA schematics. I hadn’t considered that initially, but I’m definitely going to add support for it.

Joel_Mckay 3 hours ago | parent | prev [-]

In general, there are always "better" solutions to any problem, but finding the right balance for your budget is the key.

If doing industrial work, than consumer-grade workmanship / LLM-slop is usually unacceptable. Start with the FTDI firmware tool and an isolation chip App-note...

https://www.analog.com/en/products/adm2895e-1.html

Best of luck =3

iamjackg 3 hours ago | parent [-]

Oh absolutely -- this was a no-stakes personal project, so I was happy to rely on pre-made solutions and learn a thing or two along the way.