This part of the README answers the “why” pretty well:

> Both software and hardware implementations of Wireguard already exist. However, the software performance is far below the speed of wire.

> Existing hardware approaches are both prohibitively expensive and based on proprietary, closed-source IP blocks and tools.

> The intent of this project is to bridge these gaps with an FPGA open-source implementation of Wireguard, written in SystemVerilog HDL.

So having it on an FPGA gives you the best of both worlds, speed of a hardware implementation without the concerns of a proprietary black box.