Vivado: hold my beer

Yup.

Once it took Vivado 40 minutes just to add one small Verilog file to a project. Not to compile it. Just to add it to the list of project source files, for which it scanned the file for definitions. Each time I edited the file, Vivado stalled for another 40 minutes. Same file compiled and ran all its simulation tests in Verilator (an open source tool) in a couple of seconds.

For my compiles, Vivado routinely took hours for sparse designs and over 24 hours for dense (but still conceptually small) ones. This made iteration impossible on the timescales my last FPGA project required, so I had to stop using Xilinx.

I accept that dense P&R compiles may take a long time, as it's algorithmically complex. But Vivado's occasional extremely slow and janky process for minor things left my wondering if the full P&R compile time was more due to similar bad coding issues on their side, not any real need to take that long.

Oh my lord. I'm sorry fellow tortured soul.