No, that's not what I was wondering. Cache-line size being a HW property it is not exactly "configurable", although I guess technically it could be, and I was confused how is it that the Apple sysctl returns 128B, which is a ground truth, and this paper then says that their measurements support the 64B cache-line size reported by Asahi Linux.

I think that the measurements are a hard evidence, and if they are not incorrect, why would Apple sysctl return 128B then? I am actually wondering if Apple M design really supports two different cache-line sizes, 64B and 128B respectively, but the mode is somehow configurable.