This one is especially tricky since even if you know what a phased lock loop (PLL) is, the terms CPLL and QPLL are specific to the arrangement of transceivers in these specific Xilinx FPGAs (7 series being one family of FPGAs which came before the UltraScale and then UltraScale+ series). There are four transceivers in a ‘quad’ which can either run from their ‘Channel PLL’ (CPLL) or the shared ‘Quad PLL’ that can run much faster to do basically double the line rate.

Yeah it's always tricky to decide how much detail to include in these posts. If I had gone on a whole explanation of the full 7 series GTX clocking architecture the post would easily have been another few pages in length.