That's true. The PCIe lanes on EPYC server CPUs are divided into the main Gen5 links on the SERDES (like I explained in the post) and the other lower speed lanes (Gen3/Gen4) come from the Bonus links. It is shown on the figures in the post. These Bonus links are often used for devices with lower bandwidth, like BMC. This is also true for Gigabyte MZ33-AR1, so the NVMe M.2 disk is connected to the Bonus links working at Gen3 speeds, despite the board manual says: 1 x M.2 @Gen4 (which must be a vendor's mistake).