That's cool you worked on a PA-RISC system as a job! The ISA seems clean and the later superscalar designs were very advanced for their time.

I think an updated PA-RISC design be awesome for modern workloads; huge caches with prefetch, a good branch predictor + a 8-10 wide dispatch, and some sort of vector extension. A Mix of AMD Zen+X3D & Apple ARM. To be fair, ISA doesn't matter as much really these days, any core with similar features probably would perform well.

There's always someone who thinks VLIW or a similar is a good idea. So far that's been a bit tricky for a general purpose CPU, or even some parallel designs.

* 100% personal opinion, I've never actually worked on HW design directly *