You cannot make an RS latch with 2 transistors, much less a flip-flop, which is at least 50% more complex than a latch (a flip-flop differs from a latch because its state changes only on clock transitions; this is not needed for a memory, so memories use only the simpler latches).

You can make a latch with 2 transistors and 2 resistors, but resistors are more expensive than transistors in an integrated circuit, so the minimal latch has 4 transistors.

However with simple latches you cannot build a memory, because there must be a way to address them. Therefore you must add 2 pass transistors for cell addressing, thus you end with a 6-transistor SRAM cell. In the past there have been some SRAMs with so-called 4-transistor cells, but that is a misnomer, because those were 6-transistor cells where 2 transistors were passive, having their gates connected permanently to fixed potentials, making the transistors a substitute for resistors.

A 6-T SRAM cell has a few not-so-good characteristics, so for maximum performance, like in the first-level cache memory, more complex 8-transistor SRAM cells are used.

Even the simplest SRAM cell is much more complex than a DRAM cell, flash memory cell or ROM cell.

The ideal memory cell has the area of a square whose side is double the resolution of the available photolithography, because any cell must be at the intersection of a row and a column, where the row and the column must contain at least one conductor trace.

By 3-dimensional stacking of the memory cell components, some variants of DRAM cells, including the cell from TFA, may reach the ideal memory cell size.