> The area has nothing to do with peak performance... based on the node, it has to do with the amount of components you can cram into a given space.

Of course it does. For single-threaded performance, the knobs I can turn are clockspeed (minimal area impact for higher speed standard cells, large power impact), core width (significant area impact for decoder, execution resources, etc, smaller power impact), and cache (huge area impact, smaller power impact). So if I want higher single-threaded performance on a power budget, area helps. And of course for multi-threaded performance the knobs I have are number of cores, number of memory controllers, and last-level cache size, all of which drive area. There's a reason Moore's law was so often interpreted as talking about performance and not transistor count -- transistor count gives you performance. If you're willing to build a 432 mm^2 chip instead of a 308 mm^2 chip iso-process, you're basically gaining a half-node of performance right there.

Transistor count does not equal performance. More transistors isn't necessarily going to speed up any random single-threaded bottleneck.

Again, the CRAY-1 CPU is around 42000 mm^2, so I'm guessing you'd rather run that today, right?