| ▲ | smallpipe 5 days ago |
| x86 hasn't been CISC in 3 decades anywhere but in the frontend. An architecture doesn't consume power, a design does. I'm all for shitting on intel, but getting the facts right wouldn't hurt. |
|
| ▲ | uncircle 5 days ago | parent | next [-] |
| X86 isn’t CISC, sure, but it isn’t a RISC architecture either. |
| |
| ▲ | arp242 4 days ago | parent | next [-] | | Do RISC architectures still exist? ARM has gained tons of stuff and isn't really "RISC" any more either. Maybe RISC-V? It's right there in the name, but I haven't really looked at it. However, there are no RISC-V chips that have anywhere near the performance x86 or ARM has, so it remains to be seen if RISC-V can be competitive with x86 or ARM for these types of things. RISC is one of those things that sounds nice and elegant in principle, but works out rather less well in practice. | | |
| ▲ | userbinator 4 days ago | parent | next [-] | | MIPS is as close to a "real RISC" CPU as one can be, and it's "everywhere you don't look", but for reasons entirely unrelated to performance --- it's the choice of SoCs which are too cheap for ARM. I suspect RISC-V is going to become more popular in that market, although it's one which is already filled with various Chinese MIPS/RISC-ish cores that are entirely unimpressive. | |
| ▲ | remexre 4 days ago | parent | prev [-] | | > Maybe RISC-V? RISC-V is specified as a RISC (and allows very space-/power-efficient lower-end designs with the classic RISC design), but designed with macro-op fusion in mind, which gets you closer to a CISC decoder and EUs. It's a nice place to be in tooling-wise, but it seems too early to say definitively what extensions will need to be added to get 12900K/9950X/M4 -tier performance-per-core. In either case though, a bunch of the tricks that make modern CPUs fast are ISA-independent; stuff like branch prediction or [0] don't depend on the ISA, and can "work around" needing more instructions to do certain tasks, for one side or the other. [0]: https://tavianator.com/2025/shlx.html |
| |
| ▲ | immibis 4 days ago | parent | prev [-] | | The traditional CISC and RISC division broke down the moment processors started doing more than one thing at a time. A RISC architecture was actually one with simple control flow and a CISC architecture was one with complex control flow, usually with microcode. This distinction isn't applicable to CPUs past the year 1996 or so, because it doesn't make sense to speak of a CPU having global control flow. |
|
|
| ▲ | willtemperley 4 days ago | parent | prev [-] |
| You’re contradicting yourself. The whole reason x86 burns more power is that the CISC front end can’t be avoided. |
| |
