| ▲ | ch_123 a day ago | |
This (and variations) is commonly believed but not the case - IBM's Z hardware has always used processors which natively implement the Z instruction set. I think part of the source of the confusion is a presentation from years ago which showed that some IP is shared between the Z and Power CPUs. | ||
| ▲ | sillywalk 14 hours ago | parent [-] | |
> a presentation from years ago which showed that some IP is shared between the Z and Power CPUs. The eCLIPz project, for the POWER6 & Z10[0]. "The z10 processor was co-developed with and shares many design traits with the POWER6 processor, such as fabrication technology, logic design, execution unit, floating-point units, bus technology (GX bus) and pipeline design style, i.e., a high frequency, low latency, deep (14 stages in the z10), in-order pipeline. However, the processors are quite dissimilar in other respects, such as cache hierarchy and coherency, SMP topology and protocol, and chip organization."[1] | ||