They are atomic, indeed. The underlying implementation might have used masking and shifting, especially in bit-slice implementations like KS-10, but as far as operation of the computer was concerned they were atomic.

▲

PaulHoule 5 days ago | parent [-]

It becomes problematic for multiprocessor systems but you could probably build a communications fabric and memory model that works.

My fantasy CPU lets you write to the (say) 15 bits starting at the 43rd but of a 48 bit word which a real CPU would have to do a lot of work to implement but with the right kind of cache it is probably not so bad, it also has an instruction to read a UTF-8 character at a deep pointer and increment the pointer which a real system could satisfy out of the cache except when it can’t.

	▲	p_l 5 days ago \| parent [-]
		For PDP-10, because it operated only on word values, you can easily assume that every bus and memory operation passes a full 36 bit word every time. In fact, recent-ish x86 CPUs have similar instructions, and as of Zen4 they are fast not just on Intel but also on AMD (previously they were microcoded as a bunch of shifts AFAIK with pretty lousy latency)