| ▲ | arrakark 4 days ago | |
Cache-line bursts/beats tend to be standardized to 64B in lots of NoC architectures. | ||
| ▲ | p_l 2 days ago | parent | next [-] | |
64 byte cache line size matches 64byte single burst transaction on DDR3-5, and ganged dual channel transaction on DDR2. Matching those together means you have a nice 1-to-1 relationship between filling a cache line and single fast memory transaction | ||
| ▲ | Dylan16807 4 days ago | parent | prev | next [-] | |
"Network on Chip" okay got it. | ||
| ▲ | crest 4 days ago | parent | prev [-] | |
A 64B cache-line is the same size as an AVX-512 register. | ||