modern x86 chips (for a long time really) are hybrid CISC/RISC at the hardware level. It's at the microcode that the ISA lives and that's changeable.

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cesarb 5 days ago | parent [-]

> It's at the microcode that the ISA lives and that's changeable.

No, it's not. In modern high-speed CPUs, many instructions are decoded directly, without going through the microcode engine. In fact, on several modern Intel CPUs, only one of the instruction decoders can run microcode ("complex") instructions, while all the other decoders can only run non-microcode ("simple") instructions.

It would be more precise to say that it's at the "front-end" part of the core (where the decoders are) that the ISA lives, but even that's not quite true; many ISAs have peculiarities which affect beyond that, like flags on x86.

	▲	FuriouslyAdrift 5 days ago \| parent \| next [-]
		It was my understanding that even direct coded instructions are still translated by the microcode into the actual signals to allow for errata patching since the P6 architecture and to maintain a common ISA target within a family of processors with diffferent physical characteristics.
	▲	FuriouslyAdrift 5 days ago \| parent \| prev [-]
		I think I am conflating micro-ops with microcode and your above comment is the correct way of thinking about it.