| ▲ | timewizard 21 hours ago | ||||||||||||||||
> Another problem is that each new SIMD generation requires new instruction opcodes and encodings. It requires new opcodes. It does not strictly require new encodings. Several new encodings are legacy compatible and can encode previous generations vector instructions. > so the architecture must provide enough SIMD registers to avoid register spilling. Or the architecture allows memory operands. The great joy of basic x86 encoding is that you don't actually need to put things in registers to operate on them. > Usually you also need extra control logic before the loop. For instance if the array length is less than the SIMD register width, the main SIMD loop should be skipped. What do you want? No control overhead or the speed enabled by SIMD? This isn't a flaw. This is a necessary price to achieve the efficiency you do in the main loop. | |||||||||||||||||
| ▲ | camel-cdr 21 hours ago | parent [-] | ||||||||||||||||
> The great joy of basic x86 encoding is that you don't actually need to put things in registers to operate on them. That's just spilling with fewer steps. The executed uops should be the same. | |||||||||||||||||
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