| ▲ | buildbot 7 months ago | |
People have studied the Xeon Max! Spoiler - yes, it's limited to ~23GB/s per core. It can't achieve anywhere close to the theoretical bandwidth of the HBM even, with all cores active. It's a pretty bad design in my opinion. https://www.ixpug.org/images/docs/ISC23/McCalpin_SPR_BW_limi... | ||
| ▲ | electricshampo1 7 months ago | parent [-] | |
It is integer factors better overall total BW than ddr5 spr; I think they went for minimal investment + time to market for the spr w/ hbm product rather than heavy investment to hit full bw utilization. Which may have made sense for intel overall given business context etc | ||