I've been designing chips for 2 years. One of our very well known third-party IP vendors clearly used HLS. I say clearly, because it was almost a 1:1 translation from OO C++ code, variable names, hierarchies, polymorphism, you name it. Absolutely everything about the Verilog was the complete opposite about how a designer organizes their state machines, etc.

Anyways, their IP very clearly violated the standards of a very well known interface, which could have spelled disaster at tape-out. I had to fight tooth-and-nail, and spent lots of my company's time trying to convince this third-party vendor that this was an actual issue. Only months later were they convinced. The revised code kept coming back and failing interface checks, which shows that they weren't doing these checks on their end. All I could think is, "this can't go well..."