| ▲ | lizknope 2 days ago | |
I was following this discussion on the /r/chipdesign subreddit when Ken posted there a few days ago. Nice to see that he gave credit and linked to that thread. I'm a physical design engineer that uses software from Cadence and Synopsys to do chip layout of blocks with billions of standard cells. Our flow automatically puts antenna diodes in for all block input pins. Then the tools are usually good enough to breakup internal nets with layer jumping to avoid antennas. Some of the charge also comes from the CMP process. Modern chips have about 20 layers of metal but there are lots of other via layers in between those and then all the base layers with the actual transistors. You want the wafer to be flat before building the next layer. | ||